This invention generally relates to data processing systems and more specifically to a central processor that is adapted for processing data in the form of sequences of characters.
A conventional central processor for a data processing system has a characteristic instruction set that includes program control instructions and arithmetic-logic instructions. Branch instructions and jump instructions are examples of program control instructions. Instructions for performing addition, substraction, logical AND, logical OR, and similar functions are examples of arithmetic-logic functions.
Normally such a central processor includes interruption circuitry that enables a program to be interrupted in response to some event, such as the striking of a key on an input device or the arrival of the heads of a moving head disk drive at a selected track. This circuitry, however, is not activated unitl the end of the processing cycle for the instruction then being processed; that is, when all the data operations that are defined by the instruction have been completed.
In the co-pending U.S. patent application Ser. No. 059,058 there is disclosed a central processor that is adapted to respond to additional instructions, called character string instructions, thereby to process data in the form of a sequence of characters called a character string. These character string instructions process individual characters in the string by retrieving individual characters in succession from a memory unit and, after each such retrieval, processing that character in accordance with a function defined by the character strng instruction. Thus, the central processor response to a character string instruction is an iterative process involving a retrieval and processing step for each iteration.
Conventional interruption circuitry is also operable with the instructions that are used to process character strings. However, such character string instruction defines a sequence that may involve many hundreds of thousands of iterations, each involving one or more memory transfer steps and a processing step. Therefore, the central processor may require an extraordinary amount of time to process all characters in the character string. In most applications this time will exceed the time in which the central processor should respond to the occurrence of an event. The actual time delay is called "interrupt latency", and the maximum interrupt latency for any central processor ought to approximate the interval required to process a program control or arithmetic-logic instruction involving one or two operands.
Some known central processors do process instructions that define a large number of operands. Generally these central processors receive an interruption, stop processing the instruction, and store in memory sufficient information to restart the instruction at some intermediate point after the central processor responds to the interruption. More specifically, one such central processor contains an extra bit that indicates that the instruction has been suspended at some intermediate point thereby to indicate expressly that the instruction has been suspended. Another central processor limits suspension capacility to a few instructions. These prior central processors have relatively little information that must be retained. For example, a PDP11 central processor manufactured and sold by the assignee of this invention and described in U.S. Pat. No. 3,614,740, comprises interruption circuitry that stores the "state" of the processor by transferring the program count and processor status to memory.
Character string instructions described in the copending patent application are much more complex than the instructions normally processed by such a central processor. There are many intermediate results which must be save if the instruction is to be suspended at some intermediate point and then restarted successfully at that point
None of the foregoing approaches is adapted for a solution to the problem of suspension when character string instructions are involved. For example, the addition of an extra bit to indicate expressly whether an instruction has been suspended is more costly and complex than it might seem. As previously indicated, conventional interruption techniques in the PDP11 central processor introduce unacceptable interruption latency.
Therefore, it is an object of this invention to provide a central processor in which operations in response to a specific instruction can be suspended to minimize interruption latency.
Another object of this invention is to provide a central processor that enables instructions to be suspended and subsequently restarted at an intermediate point.
Still another object of this invention is to provide a central processor that enables instructions to be suspended and that efficiently saves critical information concerning the instructions at the time that it is suspended.